International Workshop on Innovative Architecture
for Future
Generation High-Performance Processors and
Systems
Date: March 16-17, 2009
Video conference center 2F
Maui Research & Technology Center
Kihei, Maui, Hawaii
Program Committee
Prof. Atsushi Kubota, Hiroshima City U Japan
Prof. Hironori Nakajo, TUAT Japan
Prof. Peter Kogge, Notre Dame
Prof. Kiyofumi Tanaka, JAIST Japan
Prof. Hans Zima, JPL
Nikil Dutt, UCI
Jose L. Ayala, UCM Spain
Organizing Committee
Organizer: Prof. Kazuki Joe
Finance Chairs: Profs. Nicolau and Joe
Publication Chair: Prof. Veidenbaum
This invited workshop aims to bring together
researchers and designers from academia and
industry to discuss directions in the development
of high-performance, parallel, distributed,
and multimedia processors and systems. The
workshop invitees are computer architects
and compiler, operating system, and application
experts. The main goal of the workshop is
to discuss future trends in the development
of architecture and software systems and
to explore the assumptions made by the architects
about software systems and by software writers
about architecture. The increased complexity
in each of these areas calls for increased
interaction with researchers from all of
the other disciplines to accurately assess
the potential directions and future trends
in architecture and systems.
The main themes of the workshop are software-
and technology-driven and constrained new
architectures, compiler/architecture interaction
and co-design, and application requirements
and characteristics. Both numerical and non-numerical
applications, such as database, data mining,
Web- and Java-based, and (high-performance)
embedded applications, are of interest. In
all cases a longer-term view and assessment
of the future is of most interest.
This year's special focus is on multi-core
systems and ways to explore single-program
parallelism on such systems. All aspects
of design, compilation, and application design
are of interest for both single-chip multi-core
processors and multi-processor systems built
from such chips and are the 2009 special
topics.
Other topics of interest include but are
not limited to the following:
* All aspects of processor design
* Multi-threaded processors
* Large-scale multiprocessors
* Memory technology and memory hierarchy
organization
* Applications and their performance
* Power management
* Embedded system design
The workshop will consist of sessions combining
individual presentations with discussion.
Presentations will be limited to ~20 min
to provide sufficient time for discussion.
An ideal presentation will concentrate on
trends and future directions in addition
to recently obtained results. Speculation
is encouraged.
The invitees wishing to make a presentation
should submit an extended abstract, up to
3 pages, by 2/28/09. Submissions should be
electronic in pdf format. The abstracts will
be reviewed and printed in the on-site proceedigns.
The final proceedings consisting of full
papers will be published by IEEE Computer
Society Press after the meeting. The papers
will undergo an additional review process
and will be selected for publication in the
post-proceedings. Papers will be due by July
1st 2009.
Publication instructions will be distributed
by CS Press at a later date.
Hans Zima
Peter Kogge
Nikil Dutt
Jose L. Ayala
Hironori Nakajo
Atsushi Kubota
Jun Yao
Yasuhiko Nakashima
Kazuhiro Yoshimura
Kiyofumi Tanaka
Nobuyuki Yamasaki
Kazuhiro Yoshimura
Noboru Tanabe
Kazuki Joe
Session 1 (Chair: Prof. Nikil Dutt) 10:00-13:00
Mar 16
"Adaptive Fault Tolerance for Space-Borne
Computing" by Hans Zima
"An Energy-Aware Operating System and
Software Development Environment for Embedded
Systems" by Kiyofumi Tanaka, Hiroki
Zushi
"An Instruction Decomposition Method for Reconfigurable
Decoders" by Kazuhiro Yoshimura, Takashi Nakada,
Yasuhiko Nakashima:
Discussions 1
Lunch (by your own)
Session 2 (Chair: Prof. Hans Zima) 15:00-18:00
Mar 16
"Exploring the Possible Past Futures of a
Single Part Type Multi-core PIM Chip" by Peter Kogge
"Real-Time Voltage and Frequency Scaling
for Responsive Multithreaded Processor"
by Nobuyuki Yamasaki
"Hardware and Software Thermal-Aware Policies
in Embedded Processors" by Jose L. Ayala
Discussions 2
Session 3 (Chair: Prof. Jose L.Ayala) 10:00-13:00
Mar 17
"A Stage-Level Recovery Scheme in Scalable
Pipeline Modules for High Dependability" by Jun YAO
"Parallelization of FFT on Cell Broadband
Engine" by Atsushi Kubota, Kyotaro Haraoka
and Toshiaki Kitamura
"An Overview of HomeTownSimulator based
on Educational FPGA Systems" by Hironori
Nakajo and Shinobu Miwa
Discussions 3
PC meetings will be held on Mar. 15 at the
conference place.
Expected attendees will be...
Hans Zima
Peter Kogge
Nikil Dutt
Jose L. Ayala
Hironori Nakajo
Nobuyuki Yamasaki
Kiyofumi Tanaka
Atsushi Kubota
Kazuki Joe
Prof. Kazuki Joe
Prof. Alex Nicolau
Prof. Alex Veidenbaum
* Registration fee: US$300.00.
* As for the accomodation, please contact
Prof. Kazuki Joe.
* The hotel is not near the airport and there
is no shuttle service, althought a taxi can
get you there..