/*****************************************************************\
*                                                                *
*  Copyright (C) Regents of University of California, 2003       *
*  This source code is a part of EXPRESSION project and is       *
*  copyrighted by the Regents of the University of California,   *
*  Irvine.                                                       *
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/*************************************************************
 *file  : DerivedPort.h                                      *
 *authors : Asheesh Khare                                    *
 *last modified :                                            *
 *                                                           *
 *contents:contains the class definition for class UnitPort  *
 *compiled with : g++                                        *
 *for more info :                                            *
 *************************************************************/
#ifndef _DERIVED_PORT_H_
#define _DERIVED_PORT_H_


#include "GlobalIncludes.h"
#include "DerivedClassIncludes.h"
#include "Port.h"

// In this class, the pointer to Storage is null and only connections are
// valid. the connections originating from this class reach ports of "Storage"
 

class UnitPort: public Port{
public:
	UnitPort(){}
    UnitPort(PortType a) : Port(_NULL_,a){}
    ~UnitPort(){}
    UnitPort(const UnitPort &a) : Port(_NULL_,a._typeOfPort){}

    //virtual UnitPort * copy();
    virtual int is(PortType ctype)
	{ return ((ctype == _UNIT_PORT_) ? _YES_ : _NO_);}
    friend  int operator ==(const UnitPort &a, const UnitPort &b){return _NO_;}
    virtual void print(ostream &out);
    virtual int isEq(Port * ptr){return _NO_;}
    UnitPort& operator=(const UnitPort& a)
	{
     _ptrToStorage = _NULL_;
	 _connections = a._connections;
     _typeOfPort = a._typeOfPort;
     return *this;
	}
    virtual void addConnection(Connection *);

    virtual void setType(PortType a){_typeOfPort = a;}
    virtual PortType getType(){return _typeOfPort;}

    virtual void read(BaseType & a,BaseType & b);
    virtual void write(BaseType& a , BaseType & b);
    virtual void read(BaseType& value, BaseType & addr, SignalClass & latency);
	virtual void read(BaseType& value, BaseType & addr, SignalClass & latency, int memType);
    virtual void write(BaseType & data, BaseType & addr, SignalClass & latency);
};

#endif