VHDL Reference Guide

VHDL Reference Guide - Names

**Names**

Identifier	---- used in ---->	Entity Architecture Package Package Body Configuration

Syntax

See LRM section 13.3

Rules and Examples

Names (or identifiers) may consist of letters, numbers and underscore:

architecture RTL of UNIT_34 is
signal SOUND_ALARM : std_ulogic;

Case is not significant, so the following are all equivalent:

An_Example_Name
AN_EXAMPLE_NAME
an_example_name

Names must start with a letter:

signal 16_BIT_BUS : integer;   -- illegal
signal _BUS_16_BIT_ : integer; -- illegal
signal BUS_16_BIT : integer;   -- OK

Names may be of arbitary length.

None of the VHDL keywords (i.e.signal, bus, component, wait, etc.) may be reused as a name.

Synthesis Issues

Legal names (identifiers) are supported for synthesis, but long names may be truncated in some tools, or when using certain output netlist formats.

Whats New in '93

VHDL-93. supports extended identifiers. An extended identifier is delimited be backslashes(\), and may use any of the printing characters from the VHDL-93 extended character set.

This allows the use of names which would otherwise be illegal in VHDL (e.g.where compatibility with a preexisting design database is required). Examples:

\Buffer\ -- would otherwise be a keyword
\Buff\
\BUFF\	-- these are now two distinct identifiers
\BUS_$8\ -- contains otherwise illegal character

VHDL-93 has introduced the following new language keywords, whicj may not be reused as identifiers:
group, impure, inertial, literal, postponed, pure, rol, ror, shared, sla, sll, sra, srl, unaffected, xnor

these keywords should also be avoided in VHDL-87 models, to ensure upward-compatibility .