"People who are really serious about software should make their own hardware"
-- Alan Kay
Overview
In this course, we will cover how modern processors are designed to achieve high performance under which restrictions, and actually get hands-on experience with hardware design using a sequence of gently guided labs.
You will get to see your ideas actually improve performance on real metal!
We will use
RISC-V, a modern, real-world, and open-source ISA as our learnig tool.
This class will be taught mostly in-person, but
parts of it may be offered over live Zoom!
Lecturer: Sang-Woo Jun
Time:
- Lecture: Tuesdays and Thursdays, 11:00 AM - 12:20 PM (DBH 1422)
- Discussion: Fridays, 10:00 AM - 10:50 AM (PSCB 140)
Topics Covered
- Instruction sets and abstraction
- Computer Arithmetic
- Pipelining and Hazards
- Memory Hierarchy
- Introduction to modern topics
Announcements
Material
Labs
- RISC-V Assembly lab [link]
- Processor pipelining Virtualbox VM [link]
- Cache exploration [link]
Grading
- Three Labs: 60 %
- Final: 40 %
Book
This class does not have a mandatory book.
However, it may be helpful to consult
Computer Organization and Design RISC-V Edition: The Hardware Software Interface (by David A. Patterson and John L. Hennessy).
Interesting Materials
- The Digital Antiquarian, "Doing Windows" Series [link]: A fascinating history of how Microsoft Windows became what others couldn't, and how innovations in Intel 80386 helped made it happen.
- RISC-V ISA reference [link]
- Scott Meyers: Cpu Caches and Why You Care [link]: Some less obvious but serious effects of memory access patterns on performance
- Alessandro Levi: Is This the Most Complex Machine in the World? [link]: Extreme ultraviolet (EUV) machine which tries to push the limits of moore's law
- evilmonkeyzdesignz: {Taking apart an AMD chip package} [link]
- Colin Scott: Numbers every programmer should know by year [link]
- Performance Matters: AVX-512 Mask Registers, Again [link]