"People who are really serious about software should make their own hardware"
-- Alan Kay
Overview
In this course, we will cover how modern processors are designed to achieve high performance under which restrictions. We will cover the topics related to: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; memory models and synchronization; embedded systems; and parallel computers.
Since this course is a professional masters course, we will focus a bit more on pragmatic topics including architectural knowledge for performance engineering, and industry trends and outlook.
Lecturer: Sang-Woo Jun
Lectures: MW 3:30PM - 4:50PM @ ICS 174
Discussion: Fri 3PM @ ICS 174
Piazza: Link provided in Canvas
Mid-terms: TBD
Schedule And Material
| 2023-10-02 |
Lecture 1: Introduction, Moore's Law
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| 2023-10-04 |
Lecture 2: Hardware-Software Interface
- Slides - TBA
- Slides - HW-SW Interface
- Slides - RISC-V and x86
- The Digital Antiquarian, "Doing Windows" Series [link]: A fascinating history of how Microsoft Windows became what others couldn't, and how innovations in Intel 80386 helped made it happen.
- LGR, Installing MS-DOS on an AMD Ryzen Gaming PC [link]: Testament to the strict backwards-compatibility of x86!
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| 2023-10-09 |
Lecture 3: ISA Encoding and Complexity
- Slides - ISA Encoding
- Swanson Technologies, The Art of Picking Intel Registers [link]: A bit more detail into how no x86 register is quite "general-purpose"
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| 2023-10-11 |
Lecture 4: Digital Circuits Why and How
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| 2023-10-16 |
Lecture 4: Processor Design Constraints
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| 2023-10-18 |
Lecture 5: Pipelining
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| 2023-10-23 |
Lecture 5.5: Fast and Correct Pipelining
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| 2022-10-25 |
Lecture 6: Explicit Parallelism
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| 2023-11-01 |
Lecture 7: Caches and the memory system
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| 2023-11-13 |
Lecture 8: Architectural support for the Operating System
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| 2023-11-20 |
Lecture 9: Virtual Memory
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| 2023-11-27 |
Lecture 10: Multiprocessing
- Slides
- (Slightly) asymmetrical multiprocessing with ARM big.LITTLE architecture: link
- Understanding memory models is important for fast kernels (email from Linus Torvalds) link
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| 2023-12-01 |
Lecture 13: Datacenter architecture
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| 2023-12-03 |
Lecture 11: GPU Introduction
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Homework
- Homework 1: Take-home quiz, most likely
- Homework 2: Take-home quiz, most likely
Grading
Homework: 50%, midterm exam: 25%, final exam: 25% of your grade (all grades curved).
Late homework policy: You can submit late homework 5 days after the deadline for 60% of your grade.
Book
This class does not have a mandatory book.
However, it may be helpful to consult
Computer Organization and Design RISC-V Edition: The Hardware Software Interface (by David A. Patterson and John L. Hennessy).
Exam resources