Ian G. Harris

Associate Professor
University of California Irvine
Department of Computer Science
Email: harris at ics.uci.edu
Education: M.S., University of California San Diego , 1992, Ph.D., 1997.
B.S., Massachusetts Institute of Technology, 1990

RESEARCH AREAS:

Go to the System Test Laboratory for details.

  • Hardware-Software Covalidation
  • Behavioral Design Validation
  • Software Security

    • COURSES:

    CS 151 Digital Logic Design - Summer Session 1 2009

    SELECTED PUBLICATIONS:

  • Dhiraj K. Pradhan and Ian G. Harris, editors
    Practical Design Verification , Cambridge University Press, 2009
  • S. Verma and Ian G. Harris,
    SystemVerilog and Vera in a Verification Flow , book chapter in Practical Design Verification ,Cambridge University Press, 2009
  • I. G. Harris and Dhiraj Pradhan, Guest Editors
    "Design Verification and Validation" Special Section, IEEE Transactions on VLSI Systems, April 2008.
  • K. Ramineni, S. Verma, and I. G. Harris
    "Evaluation of an Efficient Control Oriented Coverage Metric" in IEEE High Level Design Validation and Test Workshop, 2008.
  • I. G. Harris,
    "INTERSTATE: A Stateful Protocol Fuzzer for SIP" in DEFCON 15 2007.
  • F. Fummi, I. G. Harris, C. Marconcini, and G. Pravadelli,
    "A CLP-based Functional ATPG for Extended FSMs" in IEEE Microprocessor Test and Verification Workshop, 2007.
  • K. Ramineni, I. G. Harris, and S. Verma,
    "Improving Feasible Interactions Among Multiple Processes" in IEEE High Level Design Validation and Test Workshop, 2007.
  • S. Verma, I. G. Harris, and K. Ramineni
    "Automatic Generation of Functional Coverage Models from CTL" in IEEE High Level Design Validation and Test Workshop, 2007.