About Me

Hi! I’m Hsin-Yu Ting, a Ph.D. candidate in the Department of Information and Computer Sciences at the University of California, Irvine (UCI), advised by Prof. Eli Bozorgzadeh.

Recently, I’m developing a hardware-software co-designed deep learning framework on an embedded FPGA-based heterogeneous SoC architecture, managing diverse computing resources to improve throughput and power efficiency. And I have experience in building acceleration system services for programmable hardware to the Android operating system, spanning framework (Java), Linux kernel (C) and hardware (Verilog) layer.

Research Interest

• Embedded ML/DL
• FPGAs in Edge Computing

Work Experience

• Software Engineering Intern: SDx Foundation Libraries, Xilinx Inc (June 2019 - Sep. 2019)
• Software Engineering Intern: I-FPGA Acceleration, Xilinx Inc (July 2018 - Sep. 2018)
• Software Engineering Intern, CADWeave (June 2017 - Sep. 2017)
• Software Engineer, ITRI (June 2015 - July 2016)
• Research Assistant, NTHU (Sep. 2014 - June 2016)

Projects

System support for FPGA acceleration service (June 2017 - present)

• Develop the software stack that integrates the operating system with programmable hardware and manages computing resources. Provide the systematic interface between the software application and FPGA designs.

FPGA-based acceleration of climate system model (Oct. 2016 - Sep. 2017)

• Design space exploration on a climate system model in high performance computing, coded in Fortran, OpenCL, C/C++. Deploy to data-rate-aware FPGA-based acceleration, providing improvement across power, performance, programmability and portability.

Rapid exploration/optimization on accelerator-rich design (Jan. 2015 - June 2016)

• A design flow to explore and detect/reduce the memory contention with customized data remapping on accelerator-rich design. Optimize and integrate the Aladdin project with Xilinx Vivado HLS tool.

Fast-prototyping many-core system (Sep. 2014 - June 2015)

• A system-level prototyping emulator, systemC transaction-level-model on the many-core platform. Application porting on mesh-based NoC and software/hardware partition.

Publications

• H.-Y. Ting, Tootiya Giyahchi, Ardalan Amiri Sani, Eli Bozorgzadeh, “Dynamic Sharing in Multi-accelerators of Neural Networks on An FPGA Edge Device,” ASAP, 2020
• H.-Y. Ting, Ardalan Amiri Sani, Eli Bozorgzadeh, “System Services for Reconfigurable Hardware Acceleration in Mobile Devices,” ReConfig, 2018
• H.-Y. Ting, C.T. Huang, “Design of Low-Cost Elliptic Curve Cryptographic Engines for Ubiquitous Security,” VLSI-DAT, 2014 (Nominated for Best Paper Award)

Professional Activities

• Member, Division of Teaching Excellence and Innovation (DTEI) Graduate Fellows Program, UCI, 2020
• Poster, Richard Newton Fellow Program, DAC, 2018 (Poster Title: “System Support for FPGA Acceleration in Mobile Devices”)

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