Nodari Sitchinava

	Karlsruhe Institute of Technology Am Fasanengarten 5 (Building 50.34, Room 207) 76131 Karlsruhe GERMANY
	Phone:	+49 721 608 46286
	Fax:	+49 721 608 43088
	email:

Research

I am a postdoctoral researcher at the Institute for Theoretical Informatics at the Karlsruhe Institute of Technology.

I have obtained my Ph.D. from the The Center for Algorithms and Theory of Computation at the Donald Bren School of Information and Computer Sciences, University of California, Irvine under the supervision of Michael T. Goodrich. After graduation I have spent two years as a postdoctoral researcher at the Center for Massive Data Algorithmics (MADALGO) at Computer Science Department of the Aarhus University.

I am interested in the design and analysis of algorithms, in particular, for multi-core architectures, external memory model, cache-oblivious model, and their parallel extensions, theoretical aspects of GPGPU computing and MapReduce framework. I am also interested in computation geometry and graph algorithms.

Curriculum Vitae

Postscript version
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Publications

Theses

N. Sitchinava "Parallel external memory model and algorithms for multicore architectures", Ph.D. Thesis, University of California, Irvine, September 2009.
N. Sitchinava "Dynamic scan chains -- a novel architecture to lower the cost of VLSI test", Master Thesis, Massachusetts Institute of Technology, September 2003.

Conference Proceedings

N. Sitchinava, N. Zeh, "A Parallel Buffer Tree", To appear in Proceedings of the 24th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA) , 2012.
M.T. Goodrich, N. Sitchinava, Q. Zhang, "Sorting, searching and simulation in the MapReduce framework", in Proceedings of the 22nd International Symposium on Algorithms and Computation (ISAAC), 2011.
D. Ajwani, N. Sitchinava, N. Zeh, "I/O-optimal algorithms for orthogonal problems for private-cache chip multiprocessors", in Proceedings of the 26th IEEE International Parallel & Distributed Processing Symposium (IPDPS), 2011.
D. Ajwani, N. Sitchinava, N. Zeh, "Geometric algorithms for private-cache chip multiprocessors", in Proceedings of the 18th European Symposium on Algorithms (ESA), 2010.
L. Arge, M.T. Goodrich, N. Sitchinava, "Parallel external memory graph algorithms", in Proceedings of the 25th IEEE International Parallel & Distributed Processing Symposium (IPDPS), 2010.
L. Arge, M.T. Goodrich, M. Nelson, N. Sitchinava, "Fundamental parallel algorithms for private-cache chip multiprocessors", in Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), 2008.
D. Eppstein, M.T. Goodrich, N. Sitchinava, "Guard placement for efficient point-in-polygon proofs", in Proceedings of the 23rd Annual ACM Symposium on Computational Geometry (SoCG), 2007.
N. Sitchinava, S. Samaranayake, R. Kapur, E. Gizdarski, F. Neuveux, T.W. Williams, "Changing scan enable during shift", in Proceedings of the 22nd IEEE VLSI Test Symposium (VTS), pp 73-78, 2004.
S. Samaranayake, E. Gizdarski, N. Sitchinava, F. Neuveux, R. Kapur, T.W. Williams, "A reconfigurable shared scan-in architecture", in Proceedings of the 21st IEEE VLSI Test Symposium (VTS), pp 9-14, 2003.

Journal Publications

S. Samaranayake, N. Sitchinava, R. Kapur, M. Amin, T.W. Williams, "Dynamic Scan: driving down the cost of test", IEEE Computer 35(10): 63-68 (2002).

Invited Talks

"A Parallel Buffer Tree", TU Eindhoven, (Host: Prof. Mark de Berg), May 4, 2012
"A Parallel Buffer Tree", MADALGO, Aarhus University (Host: Prof. Gerth Stølting Brodal), April 24, 2012
"Parallel Computing -- A Theoretical Perspective", Georgia Institute of Technology (Host: Prof. David Bader), March 17, 2011.
"Parallel Computing -- A Theoretical Perspective", Karlsruhe Institute of Technology (Host: Prof. Dr. Peter Sanders), December 21, 2010.
"Parallel Computing -- A Theoretical Perspective", Goethe University Frankfurt. (Host: Prof. Dr. Ulrich Meyer), December 20, 2010.
"Geometric algorithms for private-cache chip multiprocessors", University of California, Irvine. (Host: Prof. Michael T. Goodrich), April 30, 2010.
"Parallel external memory model for multicore architectures", Cambridge University (Host: Prof. Simon Moore), April 22, 2009.
"Parallel external memory model for multicore architectures", Dalhousie University (Host: Prof. Norbert Zeh), October 16, 2008.

Workshop Presentations

D. Ajwani, N. Sitchinava, N. Zeh. "I/O-optimal distribution sweeping on private-cache chip multiprocessors". Workshop on Massive Data Algorithmics (MASSIVE), 2011.
D. Ajwani, N. Sitchinava, N. Zeh. "Geometric algorithms for private-cache chip multiprocessors". Workshop on Massive Data Algorithmics (MASSIVE), 2010.
L. Arge, M.T. Goodrich, N. Sitchinava. "Parallel external memory model". Workshop on Theory and Many-Cores (T&MC), 2009.
N. Sitchinava, S. Samaranayake, R. Kapur, F. Neuveux, E. Gizdarski, T.W. Williams, "Dynamically reconfigurable shared scan-in architecture", IEEE International Test Synthesis Workshop (ITSW), 2004.
N. Sitchinava, S. Samaranayake, R. Kapur, F. Neuveux, E. Gizdarski, T.W. Williams, D. Spielman, "A segment identification algorithms for a dynamic scan architecture", IEEE International Test Synthesis Workshop (ITSW), 2003.
N. Sitchinava, S. Samaranayake, R. Kapur, M. Amin, T.W. Williams, "DFT - ATE solution to lower the cost of test", IEEE Workshop on Test Resource Partitioning, 2001.

Patents

Dynamically reconfigurable shared scan-in test architecture. Inventors: R. Kapur, N. Sitchinava, S. Samaranayake, E. Gizdarski, F. Neuveux, S. Duggirala, T.W. Williams. US Patents 7,836,368, 7,836,367, 7,418,640, 7,596,733, 7,743,299, 7,774,663.

Last Modified: May 30, 2012