Nodari Sitchinava
Department of Computer Science
Bren School of Information and Computer Sciences
University of California, Irvine 92697
email:
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Research
I am currently a Ph.D. student in the Theory Group at the Donald Bren
School of Information and Computer Sciences, University of California, Irvine.
My current research interests are in algorithms for multi-core architectures,
parallel external memory and cache-oblivious algorithms.
My advisor is Michael T. Goodrich.
Curriculum Vitae
Postscript version
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Publications
Theses
Conference Proceedings
- L. Arge, M.T. Goodrich, M. Nelson, N. Sitchinava, "Fundamental Parallel Algorithms for Private-Cache Chip
Multiprocessors", in Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), 2008.
- D. Eppstein, M.T. Goodrich, N. Sitchinava, "Guard placement for
efficient point-in-polygon proofs", in Proceedings of the 23rd Annual ACM Symposium on
Computational Geometry (SoCG), 2007.
- N. Sitchinava, S. Samaranayake, R. Kapur, E. Gizdarski, F.
Neuveux, T.W. Williams, "Changing scan enable
during shift", in Proceedings of
the 22nd IEEE VLSI Test
Symposium (VTS), pp 73-78, 2004.
- S. Samaranayake, E. Gizdarski, N. Sitchinava, F. Neuveux, R.
Kapur, T.W. Williams, "A Reconfigurable Shared
Scan-In Architecture",
in Proceedings of the 21st IEEE VLSI
Test Symposium (VTS),
pp 9-14, 2003.
Journal Papers
Workshop Presentations and Posters
- N. Sitchinava, S. Samaranayake, R. Kapur, F. Neuveux, E.
Gizdarski, T.W. Williams, "Dynamically reconfigurable shared scan-in
architecture", IEEE International
Test Synthesis Workshop (ITSW), 2004.
- N. Sitchinava, S. Samaranayake, R. Kapur, F. Neuveux, E.
Gizdarski, T.W. Williams, D. Spielman, "A segment identification
algorithms for a dynamic scan architecture", IEEE International Test Synthesis Workshop (ITSW),
2003.
- N. Sitchinava, S. Samaranayake, R. Kapur, M. Amin, T.W. Williams,
"DFT - ATE solution to lower the cost of test", IEEE Workshop on Test Resource Partitioning,
2001.
Publications In Preparation
- N. Sitchinava, N. Zeh, "Parallel
External Memory Computational Geometry". In preparation, 2009.
- L. Arge, M.T. Goodrich, N. Sitchinava, "Parallel
External Memory Graph Algorithms". Under submission, 2009.
- D. Eppstein, M.T. Goodrich, N. Sitchinava, "Foundational algorithms for computational
distributed robot swarms". Manuscript, 2007.
Patents
- Dynamically reconfigurable
shared scan-in test architecture. Inventors: R. Kapur, N.
Sitchinava, S. Samaranayake, E. Gizdarski, F. Neuveux, S. Duggirala,
T.W. Williams. US Patents 7,418,640 and 7,596,733 .
Last Modified: January 28, 2009