Jayram, Moorkanikara Nageswaran Phd Student in Department of Computer Science Associated with Center for Embedded Computer Systems University of California, Irvine CA 92697-3435 Address: 3069 DBH (Donald Bren Hall) e-mail: jmoorkan at uci dot edu "Fill the brain with high thoughts, highest ideals, place them day and night before you, and out of that will come great work" - Swami Vivekananda

Overview of Research Interests

I am currently working in the thesis topic related to Brain-Inspired Computing. It is an interdisciplinary topic involving the areas of Computational Neuroscience, and Computer Architecture. I have previously worked in Philips Research Eindhoven (2002-2005) in various aspects of multiprocessor system-on-chip architecture, programming and testing.

Details of statement of my research can be found here

My thesis advisor is Prof. Nikil Dutt from CECS. My coadvisor is Prof. Jeff Krichmar from the Cognitive Science Department of UCI.

Selected Works

1. A Configurable Simulation Environment for the Efficient Simulation of Large-Scale Spiking Neural Networks on Graphics Processors, Network Networks (online)
2. Computing Spike Based Convolutions on GPUs , Intl. Symposium on Circuits And Systems (ISCAS), 2009 (pdf) src code
3. Efficient Simulation of Large-Scale Spiking Neural Networks using CUDA Graphics Processors , Intl. Joint Conf. on Neural Networks (IJCNN), 2009 (Best Paper Award) (pdf) src code
4. Brain Derived Vision Algorithm on High Performance Architectures, International Journal on Parallel Programming Special Issue on Bio/Nano Applications, 2009 (online)
5. Accelerating Brain Circuit Simulations of Object Recognition with CELL Processor, International Workshop on Innovative Architectures, 2007 (pdf)
6. Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements, Parallel Computing on FPGA, 2007 (pdf)
7. MPSoC verification using a unified random program approach, Microprocessor Test and Verification, 2006 (pdf)
8. A complexity effective communication model for behavioral modeling of signal processing applications, Design Automation Conf., 2003 (pdf)
9. Cache-Coherent Heterogeneous Multiprocessing as basis for Streaming Applications, Dynamic and robust streaming in and between connected CE-devices , Book chaper in Kluwers (pdf)

1. D-mark: A Tiny DSP Processor for Efficient Implementation of Digital Filter and FFT, ASP-DAC/ Intl. Conference VLSI Design, 2002 (pdf)
2. A Scalable 8 x 8 Batcher-Banyan chips for ATM switch, ASP-DAC/ Intl. Conference VLSI Design, 2002 (pdf)

1. Brain Circuit Simulations: Computational models and Hardware Acceleration PhD Forum, Design Automation Conference (DAC 2009)
2. High-Performance Architectures for Accelerating Brain Circuit Simulations Center for Cognitive Sciences, University of California, Irvine
3. Scalable Parallel Implementations of a Brain Derived Vision Algorithm on IBM CELL processors, Joint Symposium on Neural Computation, 2007
4. WASABI: high-performance heterogenous mulitprocessor, ACACES: International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, 2005
5. Scalable Process Network Based Application Modeling For Multiprocessors, Conference on High Performance Computing in Asia Pacific Region, 2002 (paper in pdf)

1. Multiprocessor system, testing device and method for generating cache coherence testing traffic, Philips Research, Eindhoven , 2006
2. Data processing system and method for monitoring the cache coherence of processing units, Philips Research, Eindhoven , 2006

1. Application level Performance Metrics Definition and Implementation on SpaceCAKE multiprocessor, Philips Research Internal Technical note, 2003

1. CS 153: Logic Design Laboratory Course (Fall 2009), (Useful VHDL Reference)

1. Best Paper Award at International Joint Conference on Neural Networks (IJCNN 2009) link
2. UCI CECS News Letter article titled "Bridging the Gap between Neuron and Silicon", CECS e-Newletter Article 2008
3. First Place in IBM CELL University Challenge 2007. Project title: "Cluster of Sony PlayStation3's For Large-Scale Brain Modeling" (EE Times link, Press Release, Proposal, Poster)

Resume/Bio-data

I completed my undergraduate degree in Electronics and Communication Engineering from Government College of Technology, Coimbatore in India. I pursued my Master's degree in VLSI Design, Tools and Technology at Indian Institute of Technology (IIT) in New Delhi. I worked for three years as a research scientist in Philips Research Laboratories (famously called Natlab) in Eindhoven, The Netherlands. From September 2005, I started my doctoral studies here at University of California-Irvine.

A one page resume is available here

My old website is http://geocities.com/mn_jayram/.

Interests / Hobby

Check out the txt file that lists some books that I am reading, and many books that I am planning to read in the coming days. Checkout some of my brief book reviews in here

Blogs

Checkout some of my (un-edited) blogs...(TODO: hoping to clean them all soon....) http://jarjarintelluride2008.blogspot.com : Blog about the Telluride Neuromorphic Workshop 2008. http://flowingmind.blogspot.com/ : Some interesting ideas/educational videos/thoughts... http://begenet.blogspot.com/ : BeGeNet VLSI Project: Basal Ganglia Network on a Chip http://readingsnapshot.blogspot.com/ : Snapshots of technical and non-technical books from library. You be useful someday to revisit them.